In general, in many systems, it becomes necessary to perform passing of a signal between the respective parts or respective appliances which configure each system. The signal of this kind is, e.g., a data signal becoming a target to be processed, or each type of control signal. In order to accomplish an object like this, it is now widely performed to establish a connection between semiconductor chips or parts in accordance with signal passing methods (methods of receiving and delivering signals) which are referred to as “interfaces”. These interfaces define information such as transmission frequency, bit width of a data signal, configuration of each control signal, and transmission/reception protocol concerned. As the interfaces for performing the passing of a signal like this, there exist an interface where the bit width of a data signal includes a plurality of bit widths (hereinafter, referred to as “parallel interface”), and an interface where the bit width of a data signal includes only a single bit width (hereinafter, referred to as “serial interface”). Incidentally, here, the passing of a signal having a single bit width does not require that the number of signal lines is one, but includes a case as well where the transmission is performed using signals whose phases are different (e.g., mutually complementary signals with a normal phase and an opposite phase).
Conventionally, with an object of reducing the number of the signal lines, there have existed technologies on the following parallel/serial conversion and serial/parallel conversion: Namely, first, parallel signals of the parallel interface are serialized temporarily. Next, the resultant serial signal is transmitted between appliances, between parts, or between semiconductor chips by using the serial interface. Finally, the serial signal transmitted is reconstructed to the parallel signals again. Documents which can be cited as the technologies like this are as follows: Tadao Saito, “Digital Circuit”, Colona Publishing Ltd., 1982, pp. 108-110 (Prior Art 1), JP-A-6-103025 (Prior Art 2), JP-A-6-96017 (Prior Art 3), and JP-A-10-22838 (Prior Art 4).